1. Field of the Invention
Example embodiments of the present invention relate to a circuit and a method of driving a word line of memory device, and more particularly to a circuit and a method for driving a word line of a nonvolatile memory device that may be embedded in a system-on-chip (SOC).
2. Description of the Related Art
Generally, it is desirable for portable devices, for example, cellular phones etc., to be small and thin to achieve a relatively high degree of portability. Accordingly, a system-on-chip (SOC) technique may be employed to integrate a plurality of elements, for example, a central processing unit (CPU), a digital signaling processor (DSP), memory, etc., into one chip, to reduce the size of the portable device.
A memory embedded in a SOC of a portable device may include volatile memory, for example, dynamic random-access memory (DRAM) and static random-access memory (SRAM), or nonvolatile memory, for example, flash memory, etc. A flash memory device may be used to store data, for example, identification codes used in encoding and/or decoding for communication security, even when power is deactivated due to, for example, an exhausted battery, etc. A NOR-type flash memory is generally used for high speed operation in the flash memory device embedded in a SOC.
The flash memory may have three operation modes. The three operation modes may include an erase operation mode, a program operation mode and a read operation mode. A voltage level applied to a cell may be varied according to the operation mode. Accordingly, a word line voltage applied to each cell should be selectively determined according to the operation mode.
FIG. 1 is a block diagram illustrating a conventional word line driving circuit.
A word line driver may include a word line driver 10 for a read and/or program mode and a word line driver 12 for an erase mode. The word line driver 10 for the read and/or program mode may receive a read driving voltage VRD or a program driving voltage VPGM and may provide the read driving voltage VRD (e.g., about 2.6V) or the program driving voltage VPGM (e.g., about 1V) to a word line WLi through a pass transistor 14 in response to a word line enable signal WL_ENi. The word line driver 12 for an erase mode may receive an erase driving voltage VERS (e.g., about 3.3V in a read mode and about 11.5V in an erase mode) and may provide the erase driving voltage VERS to the word line WLi in response to the word line enable signal WL_ENi. Therefore, a path for transmitting the read driving voltage VRD and the program driving voltage VPGM is separated from a path for transmitting the erase driving voltage VERS by using the pass transistor 14. Accordingly, in the erase operation, a breakdown of a transistor other than a high voltage transistor may be prevented.
A control voltage signal RDDRV (e.g., about 6V) may be applied to a gate terminal of the pass transistor 14 to activate the pass transistor 14 during the read and/or program operation mode. The control voltage signal RDDRV may be generated by an internal pumping circuit at a power voltage level. In order to perform a high speed operation using a conventional device, the internal pumping circuit may operate during a standby mode prior to when the power is turned on so that the voltage level of the control voltage signal RDDRV may be increased and maintained at an operation voltage level. If the internal pumping circuit is operating during the standby mode when a read command is input, the pass transistor 12 may be substantially immediately activated to drive the word line at a higher speed.
However, in the word line driving method described above, power consumption in the standby mode may be increased due to the operation of the internal pumping circuit during the standby mode.
One conventional approach to reduce the power consumption in the standby mode is to isolate the word line driver for the read and/or program operation mode from the word line driver for the erase operation mode, instead of generating the control voltage signal RDDRV. However, according to this conventional method, the size of a word line decoder may be increased. As such, this conventional method may not be suitable for a SOC.
Another conventional approach is to generate the control voltage signal RDDRV by a self-boosting method. In the self-boosting method, the control voltage signal RDDRV may be generated quickly without using the internal pumping circuit so that the power consumption in the standby mode may not be increased. However, for example, when the read operation is performed while changing a column address without any change of a row address, the gate voltage of the pass transistor may be maintained at a floating state for a long time period. However, a node voltage may become unstable causing a malfunction in a conventional device experiencing these circumstances. The node voltage may become unstable due to leakage current, noise, etc.